A memory liquid crystal display device is a liquid crystal display device which once holds image data written into its pixels and thereafter displays the image data by carrying out a refresh operation while inverting the polarity of the image data (memory operation mode). In regular operation (normal operation mode, multicolor display mode) in which multicolor (multiple tone) display is carried out, the pixels are rewritten with new image data per frame via a data signal line, whereas in the memory operation mode, since the image data held in a memory circuit (pixel memory) is used, there is no need to supply, to the data signal line, image data for rewriting images, while the refresh operation is being carried out.
Accordingly, since the memory operation mode allows for stopping the operation of the circuit that drives the scanning signal lines and data signal lines, power consumption can be reduced. Furthermore, it is possible to reduce power consumption by (i) reducing the number of times a data signal line having a large capacity is charged and discharged and (ii) not requiring transmitting to a controller of image data that corresponds to the memory operation period.
Hence, the memory operation mode is often used for an image display which strongly requires low power consumption, such as a standby screen display of a portable phone.
FIG. 15 extracts and illustrates just a memory circuit part of a configuration of pixels in a memory liquid crystal display device as such. In a case where the pixel configuration is to be functioned also as pixels of a liquid crystal display device, assume that a liquid crystal capacitor Clc is added to the configuration, as illustrated in the broken lines in FIG. 15. A pixel configuration as such is equal to that disclosed in, for example, Patent Literature 1.
A memory circuit MR100 serving as the memory circuit part includes a switch circuit SW100, a first data storage section DS101, a data transfer section TS100, a second data storage section DS102, and a refresh output control section RS100.
The switch circuit SW100 is made up of a transistor N100 which is an N-channel TFT. The first data storage section DS101 is made up of a capacitor Ca100. The data transfer section TS100 is made up of a transistor N101 which is an N-channel TFT. The second data storage section DS102 is made up of a capacitor Cb100. The refresh output control section RS100 is made up of an inverter INV100 and a transistor N103 which is an N-channel TFT. The inverter INV100 is made up of a transistor P100 which is a P-channel TFT, and a transistor N102 which is an N-channel TFT.
Moreover, as a signal line for driving the memory circuit MR100, a data transfer control line DT100, a switch control line SC100, a high power line PH100, a low power line PL100, a refresh output control line RC100, and a capacitor line CL100 are provided for each row in a pixel matrix, and a data input line IN100 is provided for each column in the pixel matrix.
Moreover, one of drain/source terminals of a field-effect transistor such as the TFT is called a first drain/source terminal, and the other one of the drain/source terminals is called a second drain/source terminal. However, whenever it is possible to set as either one of the drain terminal or source terminal based on the direction that the electric current can flow between the first drain/source terminal and the second drain/source terminal, the terminals are called by their respective drain terminal or source terminal. A gate terminal of the transistor N100 is connected to the switch control line SC100, a first drain/source terminal of the transistor N100 is connected to the data input line IN100, and a second drain/source terminal of the transistor N100 is connected to a node PIX which is one end of the capacitor Ca100. The other end of the capacitor Ca100 is connected to the capacitor line CL100.
A gate terminal of the transistor N101 is connected to the data transfer control line DT100, a first drain/source terminal of the transistor N101 is connected to the node PIX, and a second drain/source terminal of the transistor N101 is connected to a node MRY that is one end of the capacitor Cb100. The other end of the capacitor Cb100 is connected to the capacitor line CL100.
An input terminal IP of the inverter INV100 is connected to the node MRY. A gate terminal of the transistor P100 is connected to the input terminal IP of the inverter INV100, a source terminal of the transistor P100 is connected to the high power line PH100, and a drain terminal of the transistor P100 is connected to an output terminal OP of the inverter INV100. A gate terminal of the transistor N102 is connected to the input terminal IP of the inverter INV100, a drain terminal of the transistor N102 is connected to the output terminal OP of the inverter INV100, and a source terminal of the transistor N102 is connected to the low power line PL100. A gate terminal of the transistor N103 is connected to the refresh output control line RC100, a first drain/source terminal of the transistor N103 is connected to the output terminal OP of the inverter INV100, and a second drain/source terminal of the transistor N103 is connected to the node PIX.
In a case where the liquid crystal capacitor Clc is to be provided to the memory circuit MR100 to have the memory circuit serve as a pixel, the liquid crystal capacitor Clc is to be connected between the node PIX and a common electrode COM.
Next describes an operation of the memory circuit MR100, with reference to FIG. 16.
In FIG. 16, the memory circuit MR100 is in the memory operation mode such as a standby state of a portable phone. On the data transfer control line DT100, the switch control line SC100, and the refresh output control line RC100, a potential of a binary level consisted of High (active level) and Low (non-active level) is applied from a drive circuit not illustrated. The High and Low levels of the voltage of the binary level may be set separately per line. To the data input line IN100, a binary logic level consisted of High and Low is outputted from a drive circuit not illustrated. A potential supplied by the high power line PH100 is equal to the binary logic level of High, and a potential supplied by the low power line PL100 is equal to the binary logic level of Low. A potential supplied by the capacitor line CL100 may be fixed or may vary at a given timing, however for easy explanation, the potential is fixed.
A write-in period T101 and a refresh period T102 are provided in the memory operation mode. The write-in period T101 is a period in which data to be held in the memory circuit MR100 is written in, and includes a period t101 and a period t102, consecutive in this order. In the write-in period T101, the data is written in line sequentially onto the memory circuit MR100. Hence, an end timing of the period t101 is provided for each row, within a period in which the write-in data corresponding to that row is outputted. The end timing of period t102, i.e., the end timing of the write-in period T101 is the same for all rows. The refresh period T102 is a period which holds data written onto the memory circuit MR100 in the write-in period T101, while refreshing the data; the refresh period 102 starts all at once for all rows and includes periods t103 to t110 that are consecutive in this order.
In the write-in period T101, the switch control line SC100 has a potential of High in the period t101. The data transfer control line DT100 and the refresh output control line RC100 have a potential of Low. This makes the transistor N100 be in an ON state, and thus a data potential (in this case, High) supplied to the data input line IN100 is written into the node PIX. In the period t102, the potential of the switch control line SC100 is Low. This switches the transistor N100 to an OFF state, and thus an electric charge corresponding to the data potential written in is held at the capacitor Ca100.
If the memory circuit MR100 is consisted of just the capacitor Ca100 and the transistor N100, the node PIX is in a floating state while the transistor N100 is in the OFF state. Ideally at this time, an electric charge is held at the capacitor Ca100 so that a potential of the node PIX is maintained as High. However, an actual case is that off state leakage current occurs with the transistor N100; the electric charge of the capacitor Ca100 gradually leaks outside the memory circuit MR100. Leakage of the electric charge of the capacitor Ca100 causes the potential of the node PIX to change; if the electric charge leaks for a long period of time, the potential of the node PIX changes to the degree that the data potential written in loses its original meaning.
Accordingly, the data transfer section TS100, the second data storage section DS102, and the refresh output control section RS100 are functioned so that the potential of the node PIX is refreshed and the data written in is not lost.
In order to do so, the refresh period T102 follows. In the period t103, the potential of the data transfer control line DT100 becomes High. This causes the transistor N101 to switch to the ON state, which connects the capacitor Ca100 with the capacitor Cb100 in parallel via the transistor N101. The capacitor Ca100 has its capacitance set greater than that of the capacitor Cb100. Consequently, a potential of the node MRY is made High by the movement of electric charge between the capacitor Ca100 and the capacitor Cb100. A positive electric charge moves from the capacitor Ca100 to the capacitor Cb100 via the transistor N101, until the potential of the node MRY becomes equal to the potential of the node PIX. Consequently, although the potential of the node PIX is decreased by a slight amount of voltage ΔV1 than that of the period t102, the potential is within the range of the High potential.
In the period t104, the potential of the data transfer control line DT100 becomes Low. Since this causes the transistor N101 to switch into an OFF state, an electric charge is held at the capacitor Ca100 so that the potential of the node PIX is maintained as High and an electric charge is held at the capacitor Cb100 so that the potential of the node MRY is maintained as High.
In the period t105, the potential of the refresh output control line RC100 becomes High. This switches the transistor N103 to the ON state, which thus connects the output terminal OP of the inverter INV100 to the node PIX. The output terminal OP outputs an inverted potential (Low in this case) of the potential of the node MRY, so the node PIX is charged by the inverted potential. In the period t106, the potential of the refresh output control line RC100 becomes Low. Since the transistor N103 becomes in the OFF state as a result, an electric charge is held at the capacitor Ca100 so that the potential of the node PIX is maintained as the inverted potential.
In the period t107, the potential of the data transfer control line DT100 becomes High. This switches the transistor N101 to the ON state, thereby connecting the capacitor Ca100 with the capacitor Cb100 in parallel via the transistor N101. Consequently, the potential of the node MRY becomes Low, caused by the movement of an electric charge between the capacitor Ca100 and the capacitor Cb100. A positive electric charge moves from the capacitor Cb100 to the capacitor Ca100 via the transistor N101, until the potential of the node MRY becomes equal to the potential of the node PIX. This causes an increase in the potential of the node PIX by a slight amount of voltage ΔV2 than that of the period t106, however the potential is within a range of the Low potential.
In the period t108, the potential of the data transfer control line DT100 becomes Low. This switches the transistor N101 into the OFF state, which causes an electric charge to be stored at the capacitor Ca100 so that the potential of the node PIX is maintained as Low, and causes an electric charge to be stored at the capacitor Cb100 so that the potential of the node MRY is maintained Low.
In the period t109, the potential of the refresh output control line RC100 becomes High. This switches the transistor N103 into the ON state, which connects the output terminal OP of the inverter INV100 to the node PIX. The output terminal OP outputs an inverted potential (High in this case) of the potential of the node MRY; the node PIX is charged by this inverted potential. In the period t110, the potential of the refresh output control line RC100 becomes Low. This switches the transistor N103 into the OFF state, and an electric charge is stored at the capacitor Ca100 so that the potential of the node PIX is maintained as the inverted potential.
The refresh period T102 thereafter repeats the period t103 to period t110 until a subsequent write-in period T101 starts. The potential of the node PIX is refreshed to an inverted potential in period t105, and in period t109, the potential of the node PIX is refreshed to the potential of the time when the potential was written in. In a case where a data potential of Low is to be written into the node PIX in the period t101 of the write-in period T101, the potential waveform of the node PIX becomes an inverted waveform of the potential waveform of FIG. 16.
As such, in the memory circuit MR100, the data written in is held while being refreshed, by a data inversion system. In the case where the liquid crystal capacitor Clc is added onto the memory circuit MR100, it is possible to refresh data of black display or data of white display while inverting its polarity, by inverting a potential of the common electrode COM between High and Low, at a timing at which the data is refreshed.